module handshake_pipe (
    input wire clk,
    input wire rst,

    input  wire master_valid,
    input  wire [31:0] master_data,
    output wire master_ready,

    output wire slave_valid,
    output wire [31:0] slave_data,
    input  wire slave_ready
    );


    reg ready_reg;
    reg valid_reg;
    reg [31:0] data_reg;

    always @(posedge clk) begin
        if(rst) begin
            valid_reg <= 1'b0;
        end
        else if(master_ready)begin
            valid_reg <= master_valid;
        end
        
    end

    always @(posedge clk) begin
        if(rst) begin
            data_reg <= 32'd0;
        end
        else if(master_valid & master_ready)begin
            data_reg <= master_data; 
        end
    end

    always @(posedge clk) begin
        if(rst) begin
            ready_reg <= 1'b1;
        end
        else begin
            ready_reg <= slave_ready | ~valid_reg;
        end
    end

    assign master_ready = ready_reg  ;
    assign slave_data   = data_reg   ;
    assign slave_valid  = valid_reg  ;
    

endmodule